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[Other resource] vhdl-多功能电子表

Description: 这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
Platform: | Size: 5527 | Author: 王继东 | Hits:

[VHDL-FPGA-Verilog] 数字电子钟

Description: 数字电子钟 此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能； 5. 跑表功能。-digital electronic clock this digital electronic clock with functions include : 1. Time, hours, minutes and seconds display; 2. 12 hours with 24 hours of conversion; 3. On the afternoon show; 4. Right hours, minutes, and seconds school function; 5. Stopwatch functions .
Platform: | Size: 7168 | Author: 吴健宇 | Hits:

[VHDL-FPGA-Verilog] eclock

Description: MAXPULS II 下VHDL实现多功能电子钟的源代码，包括时钟，秒表，日历等多种功能-MAXPULS II under VHDL multifunctional electronic clock source code, including the clock, stopwatch, multiple functions such as calendar
Platform: | Size: 3072 | Author: 余远恒 | Hits:

[matlab] EDA_miaobiao

Description: 《数字电路EDA入门－VHDL程序实例》---数字秒表程序例子-"digital circuit EDA portal-VHDL program examples"-- digital stopwatch procedures example
Platform: | Size: 1024 | Author: 张文 | Hits:

[File Format] VHDLEXAMPLEppt

Description: 介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern
Platform: | Size: 527360 | Author: 刘一 | Hits:

[Software Engineering] DigitalssStopwatch

Description: 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。-the stopwatch timer for the various sports competitions and requires more accurate at the various fields. This timer is a dedicated chip, using the VHDL description. In addition to its switch, the clock and display functions, but also include 1/100 seconds timer control and all the regular functions, its small size and easy to carry.
Platform: | Size: 7168 | Author: 段苛苛 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 完整的的倒计时秒表设计（指示带闪烁）ＶＨＤＬ代码，Ｑuartus 2开发环境，Archive文件，在Ｑuartus2解压即可。-Complete countdown stopwatch design (with flashing instructions) VHDL code, Quartus 2 development environment, Archive documents, in Quartus2 can extract.
Platform: | Size: 113664 | Author: 李淡 | Hits:

[VHDL-FPGA-Verilog] suzimiaobiao

Description: 这个数字秒表写的很清楚，大家如果需要我还有一些资料！~-This figure clearly written stopwatch, U.S. If you need some information I have! ~
Platform: | Size: 95232 | Author: gaoshuang | Hits:

[VHDL-FPGA-Verilog] VERILOGMIAOBIAO

Description: 秒表计时器的verilog实现，是一个教授发表的学术论文。有点参考意义。-Stopwatch timer Verilog realize, is a professor of published academic papers. Somewhat useful.
Platform: | Size: 262144 | Author: 王义 | Hits:

[VHDL-FPGA-Verilog] time

Description: vhdl语言编写秒表程序 内含每个模块的源程序-VHDL language stopwatch program includes source code for each module
Platform: | Size: 235520 | Author: BILL | Hits:

[Software Engineering] digitalclockbasedoFPGA

Description: 有时间显示与设置、秒表、闹钟、日期显示与设置功能，用6个数码管显示。 -Has the time display and settings, stopwatch, alarm clock, date display and setting function, using six digital tube display.
Platform: | Size: 211968 | Author: 卓义伟 | Hits:

[VHDL-FPGA-Verilog] 1.

Description: 用VHDL硬件描述语言完成秒表的设计，分6个模块-Using VHDL hardware description language completed stopwatch design, sub-module 6
Platform: | Size: 49152 | Author: 刘小 | Hits:

[VHDL-FPGA-Verilog] wtut_vhd

Description: 有关秒表的设计，很详细，包括测试文档，已经通过仿真。可供参考-On the stopwatch design, in great detail, including the test documents, has been through simulation. For reference
Platform: | Size: 34816 | Author: 邢继元 | Hits:

[VHDL-FPGA-Verilog] wtut_ver

Description: verilog HDL语言编写的数字秒表，仿真已经通过，可供参考-verilog HDL language digital stopwatch, simulation has already been adopted, for reference
Platform: | Size: 26624 | Author: 邢继元 | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[Embeded-SCM Develop] deCPLDVHDLshijong

Description: 基于CPLD的VHDL语言数字钟（含秒表）设计 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。 本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。 -CPLD based on the VHDL language digital clock (with stopwatch) design using a chip can be completed in addition to the clock source, buttons, speakers and display (LED) in addition to all functions of digital circuits. All digital logic functions are used in the CPLD device VHDL language. This design has a small and short design cycle (design process to achieve timing simulation), to facilitate debugging, fault rate is low and easy to modify the characteristics of the upgrade. The design uses a top-down, mixed input (input schematic- top-level file access and VHDL language input- the module program design) Design of digital clock, download and debug.
Platform: | Size: 95232 | Author: wuhuisong | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: （1）用VHDL语言编写程序，在EDA实验板上实现 （2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。 （3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。 用VHDL语言编写程序，在EDA实验板上实现 （4） 整点报时。 （5）. 闹钟功能。 （6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function.
Platform: | Size: 4096 | Author: malon | Hits:

[VHDL-FPGA-Verilog] Digital-stopwatch-design

Description: 数字秒表的设计报告，用VHDL语言编写程序，实现分析讨论中各种功能，分别进行编译并生成相应的模块，然后将这些模块连接起来形成电路图，并进行编译、仿真。-Digital stopwatch design reports, using VHDL language programming, analysis and discussion of various functions to achieve, respectively, to compile and generate the corresponding module, and then connect these modules together to form a circuit, and compiled simulation.
Platform: | Size: 375808 | Author: 吴亮 | Hits:

[VHDL-FPGA-Verilog] stopwatch-VHDL

Description: 自己用VHDL语言写的一个秒表程序，包括秒，分秒和百分秒。有程序说明和VHDL代码，一看就懂-Own use VHDL language used to write a stopwatch program, including the seconds, minutes and seconds and hundredths of a second. There description of the procedures and VHDL code, one can understand
Platform: | Size: 183296 | Author: conley | Hits:

[MiddleWare] 数字跑表VHDL

Description: 基于VHDL 实现1小时的数字跑表，包含计数器、数据存储等部分(VHDL realization of digital stopwatch based on 1 hours, including counter, data storage etc.)
Platform: | Size: 15360 | Author: zaylee | Hits:
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